Samsung has announced a strategy to accelerate the delivery of AI chips
Samsung Electronics has announced its intention to streamline the production of AI chips through its contract manufacturing division. By integrating its leading memory chip, foundry, and chip packaging services into a unified platform, Samsung aims to significantly reduce the time required for AI chip fabrication, typically by about 20%. This initiative consolidates communication channels for clients, allowing them to interface seamlessly with Samsung’s various teams involved in the chip-making process.
Speaking at a Samsung event in San Jose, California, Siyoung Choi, president and general manager of the foundry business, highlighted the transformative impact of generative AI on the technology landscape. Samsung anticipates substantial growth in the global chip industry revenue, projecting a rise to $778 billion by 2028, driven in large part by the demand for AI chips.
During a briefing with reporters prior to the event, Marco Chisari, Executive Vice President of Foundry Sales and Marketing, endorsed projections by OpenAI CEO Sam Altman regarding the escalating demand for AI chips. Altman has indicated a desire to establish approximately thirty-six new chip fabrication facilities, underscoring the industry’s burgeoning needs.
Samsung, uniquely positioned with capabilities spanning memory chips, foundry services, and chip design, believes its integrated approach will capitalize on the surging demand for AI chips. This holistic strategy aims to optimize performance and power efficiency through advanced chip architectures like gate all-around (GAA) transistors. GAA technology is pivotal as it enhances chip capabilities while mitigating power consumption, critical as chip miniaturization approaches physical limits.
While competitors like TSMC are also advancing GAA transistor technology, Samsung asserts its early adoption and plans to commence mass production of second-generation 3-nanometer GAA chips later this year. Additionally, Samsung unveiled its latest 2-nanometer chipmaking process tailored for high-performance computing, featuring innovative backside power rail placement to enhance power delivery, with mass production slated for 2027.
About The Author
